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174 lines
6.3 KiB
174 lines
6.3 KiB
; Definitions of commonly-used special memory addresses.
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;
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; These are commonly called "registers" in online documentation, even though
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; that feels like a misnomer; these aren't necessarily hardware registers in
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; the same sense as PC, A, X, Y, and so on. Despite that, I call them
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; "registers" too, since that's what everyone else calls them.
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;
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; I've often named these register definitions in the same way that they're
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; named in Yoshi's venerable snes.txt document. In some cases (where the
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; mnemonic is too obscure) I've invented a different name. In particular,
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; I've changed "ADD" to "ADDR" to reduce possible confusion between "addresses"
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; and "addition". The original name from Yoshi's doc is still listed in
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; brackets, like [CGADD], for easy cross-referencing.
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;
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; I've also heavily borrowed from Yoshi's descriptions of what these registers
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; do, though in many cases I've clarified / simplified the descriptions based
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; on my own understanding, or simply reformatted them a bit.
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; $2100: Screen display initialization [INIDISP]
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; Format: x000bbbb
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; x: 0 = screen on, 1 = screen off, bbbb: Brightness ($0-$F)
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.define INIDISP $2100
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; $2105: Screen mode register [BGMODE]
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; abcdefff a: BG4 tile size (0=8x8, 1=16x16).
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; b: BG3 tile size (0=8x8, 1=16x16).
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; c: BG2 tile size (0=8x8, 1=16x16).
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; d: BG1 tile size (0=8x8, 1=16x16).
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; e: Highest priority for BG3 in MODE 1.
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; f: MODE definition.
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.define BGMODE $2105
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; $2107-210A: BG1-4 VRAM location registers [BGxSC]
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; xxxxxxab x: Base address
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; ab: SC size
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.define BG1SC $2107
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.define BG2SC $2108
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.define BG3SC $2109
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.define BG4SC $210A
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; $210B: BG1 & BG2 VRAM location register [BG12NBA]
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; $210C: BG3 & BG4 VRAM location register [BG34NBA]
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; aaaabbbb a: Base address for BG2 (or BG4).
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; b: Base address for BG1 (or BG3).
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.define BG12NBA $210B
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.define BG34NBA $210C
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; BG1 horizontal scroll offset. [BG1HOFS]
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; BG1 vertical scroll offset. [BG1VOFS]
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; ... and similar registers for BG2-4.
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; Write to all of these twice, as they want 2 bytes of data.
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; mmmmmaaa aaaaaaaa a: Horizontal offset.
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; m: Only set with MODE 7.
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.define BG1HOFS $210D
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.define BG1VOFS $210E
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.define BG2HOFS $210F
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.define BG2VOFS $2110
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.define BG3HOFS $2111
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.define BG3VOFS $2112
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.define BG4HOFS $2113
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.define BG4VOFS $2114
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; $2115: Video port control [VMAIN]
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; i000abcd i: 0 = Address increment after writing to $2118 or reading
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; from $2139.
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; 1 = Address increment after writing to $2119 or reading
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; from $213A.
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; ab: Full graphic (see table below).
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; cd: SC increment (see table below).
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;
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; abcd Result
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; 0100 Increment by 8 for 32 times (2-bit formation).
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; 1000 Increment by 8 for 64 times (4-bit formation).
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; 1100 Increment by 8 for 128 times (8-bit formation).
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; 0000 Address increments 1x1.
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; 0001 Address increments 32x32.
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; 0010 Address increments 64x64.
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; 0011 Address increments 128x128.
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.define VMAIN $2115
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; $2116-$2117: Video port address. 2 bytes. [VMADDL/VMADDH]
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.define VMADDR $2116
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; $2118-$2119: Video port data. 2 bytes. [VMDATAL/VMDATAH]
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; According to bit 7 of VMAIN, the data can be stored as:
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; Bit 7
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; 0 Write to $2118 only. Lower 8-bits written then
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; address is increased.
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; 0 Write to $2119 then $2118. Address increased when both
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; are written to (in order).
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; 1 Write to $2119 only. Upper 8-bits written, then
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; address is increased.
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; 1 Write to $2118 then $2119. Address increased when both
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; are written to (in order).
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.define VMDATA $2118
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; $2121: Color palette selection register [CGADD]
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; Entry 0 corresponds to the SNES background color.
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.define CGADDR $2121
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; $2122: Color data register [CGDATA]
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; The palette color format is 15-bit: [0bbbbbgg][gggrrrrr].
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; You will typically write to this register twice in a row: first for the
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; low-order byte (containing green and red) and then for the high-order byte
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; (containing blue and green).
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.define CGDATA $2122
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; $212C: Main screen designation [TM]
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; 000abcde a: OBJ/OAM disable/enable.
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; b: Disable/enable BG4.
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; c: Disable/enable BG3.
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; d: Disable/enable BG2.
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; e: Disable/enable BG1.
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.define MSENABLE $212C
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; $4200: Counter enable [NMITIMEN]
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; n-vh---j n: NMI interrupt enable v: vertical counter enable
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; h: horizontal counter enable j: joypad enable
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.define NMITIMEN $4200
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; $420B: DMA enable [MDMAEN]
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; Each bit that's set enables one channel: 76543210
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.define DMAENABLE $420B
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; $4218: Joypad #1 status [JOY1L]
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; Format: AXLR0000
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.define JOY1L $4218
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; $4219: Joypad #1 status [JOY1H]
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; Format: BYsSudlr (s=select, S=start, udlr = joypad)
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.define JOY1H $4219
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; $421A: Joypad #2 status [JOY2L]
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; Format: AXLR0000
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.define JOY2L $421A
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; $421B: Joypad #2 status [JOY2H]
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; Format: BYsSudlr (s=select, S=start, udlr = joypad)
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.define JOY2H $421B
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; $43x0: DMA control for channel x. [DMAPX]
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; vh0cbaaa v: 0 = CPU memory -> PPU.
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; 1 = PPU -> CPU memory.
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; h: For HDMA only:
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; 0 = Absolute addressing.
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; 1 = Indirect addressing.
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; c: 0 = Auto address inc/decrement.
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; 1 = Fixed address (for VRAM, etc.).
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; b: 0 = Automatic increment.
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; 1 = Automatic decrement.
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; a: Transfer type:
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; 000 = 1 address write twice: LH.
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; 001 = 2 addresses: LH.
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; 010 = 1 address write once.
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; 011 = 2 addresses write twice: LLHH
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; 100 = 4 addresses: LHLH
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.define DMA0CTRL $4300
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; $43x1: DMA destination for channel x. [BBADX]
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; The upper byte is assumed to be $21, so the possible destinations are
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; $2100-$21FF.
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.define DMA0DST $4301
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; $43x2-$43x3: DMA source address for channel x. 2 bytes. [AITXL/AITXH]
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.define DMA0SRC $4302
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; $43x4: DMA source bank for channel x [AIBX]
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.define DMA0SRCBANK $4304
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; $43x5: DMA transfer size & HDMA address. 2 bytes. [DASXL/DASXH]
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; When using DMA, $43x5 defines the # of bytes to be transferred via DMA
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; itself. When using HDMA, $43x5 defines the data address ($43x5 = low byte,
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; $43x6 = hi byte).
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.define DMA0SIZE $4305
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